The continuous scaling of the physical sizes and the operating voltage of semiconductor devices in integrated circuits has dramatically increased the impact of process variations on their performance and robustness of operation. At the same time, due to the scaling of the supply and threshold voltage, transistor leakage currents have increased dramatically. This rise in leakage current may be costly, creating a new need to cool both the integrated circuit (IC) chip and the overall system.
In a stable digital circuit, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) can only operate in two states. In the ON-state, the transistor exhibits a conductive connection between its source and drain. In the OFF-state, the transistor exhibits a resistive connection between its source and drain. The current that is flowing through the transistor in this OFF-state is usually referred to as the subthreshold leakage current. This leakage current is strongly related, in an exponential relationship, to the threshold voltage (Vt) of the transistor. In bulk Complementary Metal-Oxide-Semiconductor (CMOS) technologies, a 100 mV increase in Vt may lead to a subthreshold leakage reduction by a factor of 18.
The total power consumed by all OFF transistors on a chip is called the leakage power. In many applications, this leakage power consumption has reached unacceptably high levels. It may become a significant part of the total power consumed by an Integrated Circuit (IC). In the standby mode of battery-operated mobile devices, for example, almost all of the transistors are in the OFF state, so their combined leakage current limits the duration of the standby time.
Leakage current may occur in at least three ways during the OFF state.
First, a weak inversion current may appear between the source and drain in an MOS transistor occurs when gate voltage drops below Vt. The weak inversion current may be proportional to Vt, the thermal voltage, the gate oxide capacitance, the zero bias mobility, the maximum depletion layer width, the gate oxide thickness, and the capacitance of the depletion layer. Power dissipation by the IC may heat the transistors, thereby worsening this current due to its temperature dependence.
Second, gate-induced drain leakage may occur due to a high field-effect in the drain junction of the MOS transistor. Very high and abrupt drain doping may be used to minimize gate-induced drain leakage. However, such modifications may increase the cost of fabrication of the IC.
Third, punchthrough may happen when depletion regions from the drain-substrate and source-substrate junction extend into the channel. Additional implants may be used to control punchthrough. For example, a layer of higher doping at a depth equal to the bottom of the junction depletion regions could be added. Alternatively, a halo implant could be formed at the leading edges of the drain and source junctions. However, these techniques would tend to increase the IC's cost.
There are several well known leakage reduction techniques.
First, high Vt transistors may be used on certain paths. Such transistors can produce between one and two order of magnitude of reduction in the subthreshold leakage current. However, due to their reduced capability at driving currents, high Vt transistors increase the delay of logic gates. Thus, CMOS designs having at least two thresholds may only use high Vt transistors in logic gates for non timing-critical logic paths. Timing critical paths, in contrast, would use low Vt transistors.
Alternatively, low Vt transistors could be used in the core. In this case, a large high Vt transistor could be interposed between the core and the supply, thereby acting as a power switch. In the ON-state, the core could run at a high speed because it is built from low Vt transistors. In the OFF-state, the total core would have low leakage because leakage would be limited by the power switch.
CMOS library cells for the 90 nm CMOS technology node tended to have a rather irregular layout shape. Historically, leading semiconductor companies reached this level of CMOS technology in either 2002 or 2003. By 2009, such CMOS library cells have become obsolete for leading-edge chip products.
While still somewhat irregular, CMOS library cells for the 65 nm CMOS technology node were arranged in a more orderly manner. Intel, AMD, IBM, UMC, Chartered, and TSMC all produced 65 nm ICs by September of 2007. Because of lithographic requirements linked to the reduction from 90 nm to 65 nm, fabrication of such CMOS library cells could no longer be as irregular as for the 90 nm CMOS technology node. For example, the polysilicon tracks forming the transistor gates might need to be unidirectional. As a result, such CMOS library cells would exhibit an increase in library regularity compared to CMOS library cells that were used for the 90 nm CMOS technology node. Nevertheless, such CMOS library cells would not be sufficient regular to permit efficient lithography of these cells for CMOS technology nodes significantly smaller than the 65 nm CMOS technology mode.
Thus, it would be desirable to reduce leakage current from MOSFET arrays. In particular, it would be desirable to both reduce leakage current and feature size on a fabricated IC. Moreover, it would also be beneficial to provide logic gates in a more desirable pattern to promote more efficient fabrication of the ICs.